1. Field of the Invention
The present invention relates to a power-on reset signal generating circuit and, more particularly, to a power-on reset signal generating circuit and method which prevents system malfunctions generated from an improper timing of a power-on reset signal.
2. Discussion of Related Art
FIG. 1 shows a conventional power-on reset signal generating circuit.
Referring to FIG. 1, the conventional power-on reset signal generating circuit is constructed so that a power voltage Vdd charges a condenser C1 through a resistor R1. The output at node A is inverted through an inverter INV1 and output as a signal POR. The output signal POR is at a "low" level when the charging voltage of the condenser C1 reaches above a "high" input level of the inverter INV1.
FIG. 2 shows a voltage waveform for explaining the operation of the circuit shown in FIG. 1.
Referring to FIG. 2, as the power is applied at time t=0, the level of power voltage Vdd is gradually increased and the voltage at node A reaches the "high" input level of inverter INV1 at time t=tr. Then the output of inverter INV1, which is the power-on reset signal POR, changes to a "low" level.
The level of the reset signal generated from the above-described circuit changes after a predetermined time t=tr is elapsed once the power is on at t=0. This signal level variation causes a generation of unstable reset signals, especially in microcomputer systems driven by an external oscillation clock. In such systems, the level of a reset signal generated by the conventional generating circuit can change before the external oscillation clock circuit is stabilized, resulting in system malfunctions.
In case of using a conventional external oscillator which includes a crystal resonator XL and a resistor R2 connected across the terminals of an inverter INV2 as shown in FIG. 3, the output of the conventional external oscillator behaves normally only after the time corresponding to t=ts is elapsed after the power is applied at time t=0, as shown in FIG. 4. Thus, if the reset time is shorter than time t=ts, a system malfunction occurs.
In order to solve the above-described problem, it has been suggested to increase the reset time. However, a longer reset time slows down the operation speed of the system. But if the reset time is short, the system may malfunction. Accordingly, there is a great need to address such problems of the conventional power-on reset signal generating circuit.